1. Field of the Invention
The present invention relates to a semiconductor memory equipped with redundant memory elements. More particularly, it relates to a semiconductor memory that can replace one or more defective memory elements in a regular RAM with one or more redundant memory elements in a redundant RAM which is disposed independently of the regular RAM.
2. Description of Related Art
FIG. 25 is a block diagram showing the structure of a prior art semiconductor memory. The semiconductor memory shown in FIG. 25 is a 256 Kb RAM with a 16K words×16 bits structure. In FIG. 25, reference numeral 1 denotes a regular memory cell array with 512 rows and 256 columns, reference numeral 2 denotes a redundant row line which is a redundant memory element that can replace a defective row line of the regular memory cell array, reference numeral 3 denotes a redundant column line which is a redundant memory element that can replace a defective column line of the regular memory cell array, reference numeral 4 denotes a control circuit/address buffer for buffering an input row address X<8;0> and an input column address Y<4;0> and for controlling the semiconductor memory according to a cell enable signal CEC (abbreviated as CEC signal from here on) and a write enable signal (abbreviated as WEC signal from here on) applied thereto, reference numeral 5 denotes a regular row decoder for decoding a row address XA buffered by the control circuit/address buffer 4, reference numeral 6 denotes a redundant row decoder for generating an NED (Normal Element Disable) signal at state “1” when the row address XA applied thereto matches up with an address specified by a fuse 7 intended for redundant row lines, reference numeral 8 denotes a column decoder for decoding a column address YA buffered by the control circuit/address buffer 4, reference numeral 9 denotes a column selector for connecting one of 32 pairs of bit lines to an I/O line according to a column selection signal CSEL (abbreviated as CSEL signal from here on) output from the column decoder 8, reference numeral 10 denotes a block including an I/O selector and fuse intended for redundant column lines, and reference numeral 11 denotes a data I/O circuit.
FIG. 26 is a block diagram showing connections among the components of the prior art semiconductor memory shown in FIG. 25, and shows a part of the prior art semiconductor memory which corresponds to the right half of FIG. 25 for simplicity of the drawing.
The semiconductor memory does not activate any redundant memory element when there is no defective element in the regular memory cell array 1. In this case, the regular row decoder 5 decodes a row address XA being buffered by the control circuit/address buffer 4, and then selects one row line from among the 512 row lines and sets a corresponding word line WL to “1” and sets all of remaining word lines WL to “0”. At this time, the redundant row decoder 6 outputs an NED signal at state “0” regardless of the row address XA. As a result, one row line of the regular memory cell array 1 is selected and a memory cell on the row line is connected to a bit line BL. The column decoder 8 then decodes a column address YA being buffered by the control circuit/address buffer 4, and sets a corresponding one of 32 CSEL signals to “1” and sets all of the remaining signals to “0”. As a result, a 32-to-1 multiplexer 91 of the column selector 9 connects one of the 32 pairs of bit lines to the I/O line according to the CSEL signal. A 2-to-1 multiplexer 102 of the I/O selector 10 then connects the regular I/O line to the data I/O circuit 11 disposed for every 32 row lines. As a result, the regular memory cell is connected to the data I/O circuit 11, and writing or reading of data in or from the memory cell is done (i.e., the memory cell is accessed). When reading data from the memory cell a sense amplifier/write driver 111 amplifies an electric charge on the bit line BL connected to the data I/O circuit 11, whereas when writing data in the memory cell the sense amplifier/write driver 111 sends data applied thereto onto the bit line BL connected to the data I/O circuit 11 and writes the data in the memory cell.
When there is a row defect in the regular memory cell array 1, an enable fuse FEN (not shown in the figure) in the fuse 7 intended for redundant row lines and an address fuse FXAi (not shown in the figure) corresponding to the address of the defective row line are cut by using a laser trimming apparatus. As a result, a corresponding fuse determination circuit (not shown in the figure) in the fuse 7 intended for redundant row lines outputs FENO and FXAiO signals at state “1”. In contrast, any other fuse determination circuit corresponding to a fuse which has been not cut sends out a signal at state “0”.
The redundant row decoder 6 outputs an NED signal at state “1” when the input row address XA matches up with the address of a defective row line (i.e., the FXAiO signal) which is programmed into the address fuse FXAi. The regular row decoder 5 sets all outputs to “0” in response to the NED signal. As a result, the redundant row line 2 is connected to a bit line BL. After that, one of the 32 pairs of bit lines is connected to the I/O line and the data I/O circuit 11, as in the case where there is no defective memory cell in the regular memory cell array 1, and a specified memory cell within the redundant row line 2 is accessed. When the row address XA does not match up with any defective row address programmed to each fuse FXAi, the redundant row decoder 6 outputs the NED signal at state “0”. Therefore, in this case the regular row decoder 5 operates as in the case where there is no defective memory cell in the regular memory cell array 1, and a regular memory cell specified by the row address XA and the column address YA is accessed.
When there is a column defect in the regular memory cell array 1, fuses FY corresponding to a set of 32 column lines including the defective column line within the fuse 101 intended for redundant column lines are cut by using a laser trimming apparatus. As a result, the fuse determination circuit (not shown in the figure) within the fuse 101 intended for redundant column lines outputs an FYr (r=0 to 15) signal at state “1”. In contrast, other fuse determination circuits corresponding to fuses which have been not cut output FYr signals at state “1”. The column decoder 8 decodes the column address YA being buffered by the control circuit/address buffer 4, and sets a corresponding one of the 32 CSEL signals to “1” and sets all of the remaining CESL signals to “0”. As a result, the 32-to-1 multiplexer 92 intended for redundant column lines of the column selector 9 connects a corresponding one of the 32 pairs of bit lines to the I/O line associated with redundant column lines according to the CSEL signal. The 2-to-1 multiplexer 102 of the I/O selector 10 receives the outputs FYr of the fuse determination circuits within the fuse 101 intended for redundant column lines, and connects the I/O line associated with redundant column lines to the data I/O circuit 11 corresponding to the set of 32 column lines including the defective column line and also connects the regular I/O line to the other data I/O circuits 11. The word line selection is carried out as in the case where there is no defective memory cell in the regular memory cell array 1 and in the case where there is a row defect in the regular memory cell array 1. Thus, the redundant column line 3 is accessed in place of the set of 32 column lines including the defective column line.
When there is a single bit defect in the regular memory cell array 1, it is possible to repair it by using either the redundant row line 2 or the redundant column line 3.
FIG. 27 is a schematic diagram showing the structure of a prior art semiconductor memory with a variable-size redundant replacement structure as disclosed in Japanese patent application publication (TOKKAIHEI) No. 10-275497. In the figure, reference numeral 60 denotes a 256 Mb DRAM chip which is the prior art semiconductor memory, reference numeral 61 denotes a 16 Mb unit, reference numeral 62 denotes a 1 Mb block, reference numeral 63 denotes a main 16 Mb array that contains sixteen 1 Mb blocks 62, reference numeral 64 denotes a 128 Kb redundant block, reference numeral 65 denotes a redundant unit control circuit, reference numeral 67 denotes an NMOS device that constitutes a memory cell in cooperation with a capacitor 66, reference numeral 68 denotes a sense amplifier, reference numeral 70 denotes an NMOS device which constitutes a redundant memory cell in cooperation with a capacitor 69, and reference numeral 71 denotes a sense amplifier.
As shown in FIG. 27, the 256 Mb DRAM chip 60 consists of the sixteen 16 Mb units 61, and each 16 Mb unit 61 delimits an area of thereof in which a defect which can be repaired can be caused. Each 16 Mb unit 61 has a main 16 Mb array 63 that consists of sixteen 1 Mb blocks (subarrays) 62, a 128 Kb redundant block 64, and a redundant unit control circuit 65, and each 1 Mb block 62 has 1M cells. While each 1 Mb block 62 includes 512 word lines WL, when a specific 1 Mb block 62 is activated, only one word line WL is selected and a capacitive charge on a corresponding capacitor 66 is sent to a corresponding bit line by way of a corresponding NMOS device 67. A corresponding sense amplifier 68 then amplifies the electric charge on the bit line BL. The amplified bit information is selected by a corresponding column address (not shown in the figure), and is sent to a data output circuit (also not shown in the figure).
Each 1 Mb block 62 has no redundant word line. For the sake of repairing a defect of the 16 Mb unit 61, the 128 Kb redundant blocks 64 provided with sixteen variable-size redundant units RU0 to RU15 is designed to replace the defect that resides in any one of the sixteen 1 Mb blocks 62. Each of the redundant units RU0 to RU7 contains a single redundant word line, each of the redundant units RU8 to RU11 contains two redundant word lines, each of the redundant units RU12 and RU13 contains four redundant word lines, and the redundant units RU14 and RU15 contain eight and thirty-two redundant word lines, respectively.
When the redundant unit control circuit 65 is enabled, all of 8,192 word lines WL within the main 16 Mb array 63 are disabled. Instead, one of the 64 redundant word lines within the 128 Kb redundant block 64 is activated. As a result, a capacitive charge on a corresponding capacitor 69 is sent to a corresponding bit line by way of a corresponding NMOS device 70. A corresponding sense amplifier 71 then amplifies the electric charge on the bit line BL. The amplified bit information is selected by a corresponding column address (not shown in the figure), and is sent to a data output circuit (also not shown in the figure).
A problem with a prior art semiconductor memory constructed as mentioned above is that since a regular memory cell array and a redundant block are not disposed independently of each other, and whenever the structure of the regular memory cell array or the structure of the redundant block is changed, it is necessary to design the entire semiconductor memory again, a lot of design time, especially time required for layout design is needed and the design cost is increased. Moreover, another problem is that when increasing or decreasing the number of memory elements included in the redundant block according to the scale of the semiconductor memory or the defect density caused by a wafer production line, it is necessary to do the design of the entire semiconductor memory again, and the re-designing counts against ASICs which require a short design time.
In addition, since a row or column line, which can be replaced, is limited to the one in a regular memory cell array which shares bit lines and a word line with another line in the prior art semiconductor memory shown in FIGS. 25 and 26, although when there are two defects, for example, it is possible to repair them if the two defective lines are located in the right-hand and left-hand sides of the regular memory cell array, respectively, it is impossible to repair them if the two defective lines are located in only one of the right-hand and left-hand sides of the regular memory cell array. In other words, the effective use of the redundant memory element is not performed, and the yield improvement efficiency is bad.
Furthermore, since in the prior art semiconductor memory shown in FIG. 27 a redundant block can repair only defective lines included in a 16 Mb unit in which the redundant block is disposed, when three sets of 32 defective row lines are concentrated on one 16 Mb unit, for example, a corresponding redundant block is not able to repair these defective row lines. In addition, another problem is that since a defective zone can be replaced only by one zone having the same shape as the defective zone within a redundant block, it is impossible to do replacement with efficiency.